Research Institutes

In the area of Wafer Processing & MEMS Technologies the IZM works on:

Multi Device Integration

Increasing complexity and miniaturization of innovative products lead to the fact that system integration will be getting more and more important for the scientific and technical development. The Fraunhofer IZM in Chemnitz is mainly focused on Research and Development in the fields of smart system integration in Germany, Europe and world wide.

The micro and nanosystem technologies as well as electronics are playing a key role in todays product development and industrial progress. They enable the integration of mechanical, electrical, optical, chemical, biological and other functions into a very small space with dimensions ranging from sub micrometers up to some millimeters. Combined with intelligence, power supply and communication ability these systems are multi device integrated and should be developed for use inside the host. System integration will determine the economic success of manufacturers and users coming from consumer electronics, telecommunication, mechanical engineering, medical technology, and automotive in a high degree. To keep long term competitiveness a sophisticated technological potential is necessary. The Fraunhofer IZM positions itself to these challenges and takes part very actively in the further development of Smart System Integration and the needful gap bridging from NANO to MICRO and to the MACRO world.

Si-Technology and Vertical System Integration

The Si Technology and Vertical System Integration Department includes the Wafer Technology and Process and Design Integration Groups: The department's task areas are the process integration of new materials and processes for silicon-based semiconductor technology, as well as the development and optimization of CMOS-compatible technologies for the fabrication of three-dimensional integrated microelectronic systems (Vertical System Integration – VSI®).

VSI® offers system manufacturers maximum flexibility in the application of existing mainstream technologies, combined with maximum density of electronic functionality. Component assemblies, fabricated and tested separately, are vertically integrated into a single 3D chip using standard CMOS-compatible wafer fabrication processes.

New processes and materials in semiconductor technology, such as for example strained Si or SiGe layer epitaxy, are integrated into an overall process from the standpoint of performance improvement and the low-cost fabrication of microelectronic systems, and evaluated with appropriate test structures.

High Density Interconnect and Wafer Level Packaging

The department is focusing on the development and application of thin-film processes in microelectronic packaging. Production-compatible equipment and technological expertise support thin film processing in a 800 mｲ clean room. The department cooperates world-wide with manufacturers and users of microelectronic products, with clean room equipment producers and material developers from the chemical industry.

Three well-established technology branches offer prototyping and small-volume production as a regular service within the realms of MCM-D, waferlevel CSP with redistribution routing and wafer-level bumping for flip chip mounting to both industrial partners and customers. Processable wafer size is limited from 100 mm to 200 mm. In cooperation with some equipment manufacturers, 300 mm tools are being introduced step by step. The service in the above areas can also include a technology transfer even to customer-specific tools. Beyond the regular service technology, the department is engaged in numerous R&D projects, whereby ongoing skills and know-how are being developed, which could be applied together with SME-partners on a development stage. Among the main topics are integrating passive components into high density circuits, MCMs or wafer level packages and the mobile power supply for microsystems.